A flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) device includes an array of cells that can be independently programmed and read. As a result, a group of the cells must be erased together as a block. A flash memory device of this type includes individual Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) memory cells, each of which includes a source, a drain, a charge storage layer and a control gate to which various voltages are applied to thereby program the cell with a binary 1 or 0, to read the cell, to erase all or some of the cells as a block, to verify that the cell is erased or to verify that the cell is not over-erased.
Memory cells in a flash memory device are typically connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective word line and the drains of the cells in a column being connected to a respective bit line. The sources of all the cells in a column are connected to another bit line.
A cell is typically programmed by applying a voltage to the control gate, applying a voltage to the drain and grounding the source. A cell is typically read by applying a voltage to the word line to which the control gate of the cell is connected, applying a voltage to the bit line to which the drain of the cell is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high, the bit line current will be zero or nearly zero. If the cell is not programmed or erased, the threshold voltage will be relatively low, the control gate voltage will invert the channel, and the bit line current will be relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying a voltage to the P-well (substrate) and a negative voltage to the control gate, while allowing the source/drain to float. In another arrangement, a cell may be erased by applying a relatively high voltage to the source (or drain), a negative voltage to the control gate and allowing the drain (or source) to float. These applied voltages cause the electrons that were injected into the charge trapping layer during programming to undergo either Fowler-Nordheim tunneling or hot hole neutralization through the thin tunnel oxide layer to either the substrate (P-well) or the source/drain depending on the type of erase being performed.
More specifically, during program and read operations only one word line connected to the control gates of a row of cells is held high at a time, while the other word lines are grounded. A positive voltage is applied to the drains of all of the cells and if the threshold voltage of an unselected cell is zero or negative, the leakage current will flow through the source, channel and drain of the cell.
The undesirable effect of the leakage current from the over-erased cells is as follows. In a typical flash EEPROM, the drains of a large number of memory cells, for example 512 cells are connected to each bit line. If a substantial number of cells on the bit line are drawing background leakage current, the total leakage current on the bit line can exceed the cell read current. This makes it impossible to read the state of any cell on the bit line and therefore renders the memory inoperative.
Because the background leakage current of a cell varies as a function of threshold voltage, the lower (more negative) the threshold voltage, the higher the leakage current. It is therefore desirable to prevent cells from being over-erased by reducing the threshold voltage distribution to as low a range as possible, with ideally all cells having the same threshold voltage after erase.